Last updated on February 26, 2023 by Dan Nanni
Makefile is a text file that contains a set of rules that specify how to build a program or a set of files. Makefile is used by the
make utility to automate the build process and manage dependencies between files. The
make utility reads the Makefile and executes the rules in order to build the target files, which can be executables, libraries, or other files.
A typical Makefile consists of a set of rules, each of which defines how to build a target file. Each rule consists of (i) a target, (ii) a list of dependencies, and (iii) a set of commands to execute in order to build the target file. The
make utility automatically determines the order in which the rules should be executed based on the dependencies between files.
There are several pre-defined built-in variables used by
make. One of them is "$<". To explain what it is, see the Makefile rule example below.
foo.o: foo.c bar.h baz.h gcc -o $<
In this Makefile rule,
foo.o is a target file to build, and it depends on three files:
baz.h. This means that, if any of these files in the dependency list is updated, the
make will invoke the command listed below, which is "gcc -o $<".
So what is this thing: "$<"?
In Makefile, "$<" is a special variable that represents the first dependency of a rule. In this example,
foo.o depends on three files, and the first dependency is
foo.c. So "$<" refers to
foo.c. Even though this rule has additional dependencies like
baz.h, "$<" still refers to
foo.c, since it represents the first dependency listed in the rule.
"$<" is just one of several special variables that can be used in Makefiles. Some other commonly used special variables include "$@" (the target of the rule), "$^" (all dependencies of the rule), and "$*" (the stem of the target, i.e., the part before the file extension). The exact set of special variables available in a given Makefile may depend on the version of Make being used and any extensions or macros defined in the Makefile itself.
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